Sample and hold circuits typically employ switching device for periodically connecting a capacitor to an input signal to be sampled so that while the capacitor is connected to the signal it charges and discharges to track the voltage level of the signal. After the switch disconnects the capacitor from the input signal, the capacitor holds that voltage level existing at the time it is disconnected.
The capacitor is also typically connected to a high impedance input of a buffer amplifier which provides the hold output signal of the sample and hold circuit, the high impedance input ensuring minimal discharge of the capacitor during the hold phase of the circuit operation.
See U. S. Pat. No. 4,584,559 issued April 22, 1986 to Penney for discussion of a sample and hold circuit used to eliminate glitches on the output of a digital-to-analog converter. Sample and hold circuits are also often used on the input of an analog-to-digital converter for providing a stable input signal for the converter.
The switches used in sample and hold circuits are typically either Schottky diode bridges or field-effect transistors. For an example of an elaborate sample and hold circuit using the latter type of switching device, see U. S. Pat. No. 3,820,033 issued June 25, 1974 to Iwata.
Such prior devices may generally be made simply and are effective for high speed applications. However, they cannot be produced using high speed bipolar integrated circuit processes. Conventional sample and hold circuits cannot be made with bipolar transistors, particularly NPN transistors, because they require longer settling times during switching. Thus, they typically are inadequate for high speed applications.